1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to electrically programmable memory devices with improved programmability.
2. Description of the Related Art
Electronically programmable read only memory (EPROM), erasable electronically programmable read only memory (EEPROM) and Flash memory are classes of floating gate memory devices. More particularly, these floating gate memory devices are programmable memory devices which use floating gates as charge storage layers.
In recent years, techniques have been developed to increase the programming speed for floating gate memories. In particular, U.S. Pat. No. 5,615,153 describes an approach to increase programming speed by increasing wordline (gate voltages) while source voltage is held constant, and is hereby incorporated by reference. By starting at a lower wordline voltage, and increasing the wordline voltage to a higher wordline voltage during programming, programming speed is increased and a high final turn-on threshold voltage can be achieved.
While this approach is able to increase programming speed, there are still several disadvantages. One disadvantage is that threshold voltage distribution difficulties can result when fast programming is performed. Another disadvantage is that programming of floating gate memories has been done in small programming steps wherein after the completion of each programming step a verifying operation must be performed to determine the validity of the last programming step. The verifying operation has typically been done as a separate operation. For example, such repetitive programming techniques are further described in U.S. Pat. No. 5,172,338 and U.S. Pat. No. 5,220,531. As a result, these conventional repetitive programming techniques require a long time for programming to complete largely because of the inefficiency of having to switch between a programming mode of operation and a verify mode of operation after each programming step.
In the view of the foregoing, there is a need for faster and more efficient schemes for programming electrically programmable memory cells.